Design of a 10-bit, 5 Ms/S Pipelined ADC for CMOS Image Sensor
IR@CEERI: CSIR-Central Electronics Engineering Research Institute, Pilani
View Archive Info| Field | Value | |
| Title |
Design of a 10-bit, 5 Ms/S Pipelined ADC for CMOS Image Sensor
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| Creator |
Behera, KC
Santosh, M Bose, SC |
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| Subject |
IC Design
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| Description |
In this paper design of a 10bit, 5MS/s pipelined ADC suitable for chip level integration of CMOS image sensors has been attempted. The designed pipeline ADC is simulated in 3.3 V, double poly, triple metal 0.35 μm Austria Microsystems process. The maximum DNL and INL of the designed pipeline ADC are -1/+0.5LSB and -2.5/+1.75LSB respectively. The dynamic input range of the ADC is 3 V. The designed ADC eliminates the need of front end S/H circuit, thereby reducing the chip area and power. The designed pipeline ADC consumes a power of 40mW and chip area of only 0.49 mm2. The offset cancellation of the S/H circuit and the Multiplying Digital-to-Analog circuit (MDAC) are done by the use of a simple offset cancellation switch.
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| Date |
2010
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| Type |
Conference or Workshop Item
PeerReviewed |
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| Format |
application/pdf
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| Identifier |
http://ceeri.csircentral.net/73/1/04_2010.pdf
Behera, KC and Santosh, M and Bose, SC (2010) Design of a 10-bit, 5 Ms/S Pipelined ADC for CMOS Image Sensor. In: 14th VLSI Design and Test Symposium (IEEE/VSI VDAT 2010), July 7-9, 2010, Chitkara University Campus, Himachal Pradesh. (Submitted) |
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| Relation |
http://ceeri.csircentral.net/73/
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