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DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold Operation

IR@CEERI: CSIR-Central Electronics Engineering Research Institute, Pilani

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Field Value
 
Title DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold Operation
 
Creator Rajput, KK
Saini, AK
Bose, SC
 
Subject IC Design
 
Description This work presents the rigorous formulation of input referred offset voltage for differential amplifier, having the input pair devices in subthreshold region of operation. The formulation has been verified in 0.35 μm and 0.18 μm CMOS technologies by using Monte Carlo Simulation. Minimization of 1/f noise is the additional advantage of this method.
 
Date 2010
 
Type Conference or Workshop Item
PeerReviewed
 
Format application/pdf
 
Identifier http://ceeri.csircentral.net/90/1/03_2010.pdf
Rajput, KK and Saini, AK and Bose, SC (2010) DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold Operation. In: IEEE Computer Society Annual Symposium on VLSI, July 5-7, 2010, Lixouri Kefalonia, Greece. (Submitted)
 
Relation http://ceeri.csircentral.net/90/