VLSI Architecture of Exponential Block for Non-Linear SVM Classification
IR@CEERI: CSIR-Central Electronics Engineering Research Institute, Pilani
View Archive Info| Field | Value | |
| Title |
VLSI Architecture of Exponential Block for Non-Linear SVM Classification
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| Creator |
Saurav, S
Singh, S Saini, AK Saini, R Gupta, S |
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| Subject |
IC Design
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| Description |
In this work, we present a dedicated hardware implementation of exponential function computation unit using CORDIC (Coordinate Rotation Digital Computer) algorithm for extended range of input arguments. Hardware architecture design is done keeping in view its possible integration in the hardware implementation of the Radial Basis Function (RBF) based Support Vector Machine (SVM) classifier. The designed architecture is prototyped on a field programmable gate array (FPGA) to meet the specific requirement of performance. The proposed design is operating at a maximum clock frequency of 249 MHz. This shows good performance of our proposed architecture in terms of speed. Synthesis result also reveals that the proposed architecture is resource efficient.
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| Date |
2015
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| Type |
Conference or Workshop Item
PeerReviewed |
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| Format |
application/pdf
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| Identifier |
http://ceeri.csircentral.net/244/1/9_2015%281%29.pdf
Saurav, S and Singh, S and Saini, AK and Saini, R and Gupta, S (2015) VLSI Architecture of Exponential Block for Non-Linear SVM Classification. In: 4th International Conference on Advances in Computing, Communications & Informatics (ICACCI-2015), August 10-13, 2015, SCMS, Aluva, Kochi. (Submitted) |
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| Relation |
http://ceeri.csircentral.net/244/
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