An Improved Highly Efficient Low Input Voltage Charge Pump Circuit
IR@CEERI: CSIR-Central Electronics Engineering Research Institute, Pilani
View Archive Info| Field | Value | |
| Title |
An Improved Highly Efficient Low Input Voltage Charge
Pump Circuit
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| Creator |
Kumar, N
Gudlavalleti, RH Bose, SC |
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| Subject |
IC Design
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| Description |
Conventional charge pump circuit based on dynamic charge transfer switch (CTS) is limited by its efficiency due to the threshold voltage of MOS transistor. This paper proposes an improved dynamic CTS based charge pump circuit by modifying the conventional circuit architecture at the output stage by a PMOS transistor with appropriate control signals. A four-stage dynamic CTS based charge pump circuit with pumping capacitance of 50 pF, clock frequency of 20 MHz and load current of 100 µA is designed and simulated in Cadence environment using UMC 0.18 µm CMOS technology. As compared to conven-tional architecture, this modification has reduced the voltage loss at the output to 1.3% as compared to 9% for 1 V input and 6% as compared to 20% for 0.3 V input voltage. The core dimension of the layout is 750 µm × 530 µm.
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| Date |
2017
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| Type |
Conference or Workshop Item
PeerReviewed |
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| Format |
application/pdf
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| Identifier |
http://ceeri.csircentral.net/300/1/05-2017.pdf
Kumar, N and Gudlavalleti, RH and Bose, SC (2017) An Improved Highly Efficient Low Input Voltage Charge Pump Circuit. In: 21st VLSI Design and Test Symposium (VDAT-2017), 29 June 2017 - 02 July 2017, Roorkee. (Submitted) |
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| Relation |
http://ceeri.csircentral.net/300/
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