A Lifting Instruction for Performing DWT in LEON3 Processor based System-on-Chip
IR@CEERI: CSIR-Central Electronics Engineering Research Institute, Pilani
View Archive Info| Field | Value | |
| Title |
A Lifting Instruction for Performing DWT in LEON3 Processor based System-on-Chip
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| Creator |
Bansal, R
Jatav, MK Karmakar, A |
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| Subject |
IC Design
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| Description |
Discrete Wavelet Transform (DWT) calculations form an inherent part of many signal processing applications. Application specific instructions provide a means to increase performance and efficiency of System-on-Chip (SoC) requiring DWT operations. In this paper, lifting scheme based hardware for efficient DWT calculation, is implemented as an instruction to enhance the performance of an SoC. The hardware is integrated using the coprocessor interface of the SPARCv8 ISA based LEON3 processor. This method for attaching lifting hardware is found to be much more efficient than the prevalent system-bus based integration. The performance measure is provided in terms of CPI and MIPS along with FPGA and ASIC implementation results of the SoC.
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| Date |
2017
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| Type |
Conference or Workshop Item
PeerReviewed |
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| Format |
application/pdf
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| Identifier |
http://ceeri.csircentral.net/306/1/09-2017.pdf
Bansal, R and Jatav, MK and Karmakar, A (2017) A Lifting Instruction for Performing DWT in LEON3 Processor based System-on-Chip. In: 21st VLSI Design and Test Symposium (VDAT-2017), 29 June 2017 - 02 July 2017, Roorkee. (Submitted) |
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| Relation |
http://ceeri.csircentral.net/306/
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