A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher
IR@CEERI: CSIR-Central Electronics Engineering Research Institute, Pilani
View Archive Info| Field | Value | |
| Title |
A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher
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| Creator |
Pandey, JG
Goel, T Karmakar, A |
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| Subject |
Embedded Systems
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| Description |
Abstract— Security and privacy are the prime concern in the emerging internet of things (IoT) and cyber-physical systems (CPS) based applications. Lightweight cryptography plays an essential role for securing the data in this emerging pervasive computing environ ments. In this paper, we propose a high- performance and area-efficient VLSI architecture with 64-bit datapath for the PRESENT block cipher. The proposed architecture performs an integrated encryption/decryption operation for both 80-bit and 128-bit key lengths. The architecture is synthesized for the Yirtex-5 XCSVLX 1 10T FPGA device, available on the Xilinx ML-505 platform. It has been observed that the proposed architecture utilizes 0.73% and 0.87% of FPGA slices for 80-bit and 128-bit key lengths respectively. A through put of 410 Mbps and power consumption is about 16 mW for both the key lengths.
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| Date |
2019-11-29
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| Type |
Conference or Workshop Item
PeerReviewed |
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| Format |
application/pdf
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| Identifier |
http://ceeri.csircentral.net/327/1/21-2017.pdf
Pandey, JG and Goel, T and Karmakar, A (2019) A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher. In: 17th international Conference on Embedded Systems & 31st International Conference on VLSI Design, Jan. 6-10, 2018, Pune, Maharashtra. (Submitted) |
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| Relation |
http://ceeri.csircentral.net/327/
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