A Novel Design of SRAM using Memristors at 45 nm Technology
IR@CEERI: CSIR-Central Electronics Engineering Research Institute, Pilani
View Archive Info| Field | Value | |
| Title |
A Novel Design of SRAM using Memristors at 45 nm
Technology
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| Creator |
Louis, VJ
Pandey, JG |
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| Subject |
IC Design
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| Description |
There is an ever-increasing need for low-cost, higher density, low-power and high-performance memory devices. Memristor is one of the most promising device for obtaining memories as it offers smaller area and lower con-sumption. In the proposed work memristor-based SRAM circuit has been de-signed by using 45 nm technology of Predictive Technology Model. The read time of 1-bit cell is 5 ps and the write time 7 ps. Total area of the cell is 3.861 micrometer square.
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| Date |
2019
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| Type |
Conference or Workshop Item
PeerReviewed |
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| Format |
application/pdf
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| Identifier |
http://ceeri.csircentral.net/462/1/042019.pdf
Louis, VJ and Pandey, JG (2019) A Novel Design of SRAM using Memristors at 45 nm Technology. In: 23rd International Symosium on VLSI Design and Test (VDAT-2019), July 04-06, 2019, IIT Indore, India. |
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| Relation |
http://ceeri.csircentral.net/462/
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