Reconfigurable Digital Logic Gate based on Neuromorphic Approach
IR@CEERI: CSIR-Central Electronics Engineering Research Institute, Pilani
View Archive Info| Field | Value | |
| Title |
Reconfigurable Digital Logic Gate based on Neuromorphic Approach
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| Creator |
Singhal, N
Santosh, M Bose, SC |
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| Subject |
IC Design
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| Description |
This paper presents low power and highly tuneable LIF (modified) neuron model and its usage to implement reconfigurable digital logic gate. Simulations are done using Tower Jazz Semiconductor's 180nm technology and UMC 28 nm technology in Cadence virtuoso environment. Results show the advantage of neuromorphic approach in terms of re-configurability, power and area when compared to traditional logic gate designs. Reconfigurable gate performs AND/OR/NAND/NOR/XOR/XNOR. It works for both spiking input as well as DC input (current signal). Power consumption of reconfigurable gate designed using modified LIF is at least 45% less than the power consumption of CMOS gates.
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| Date |
2019
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| Type |
Conference or Workshop Item
PeerReviewed |
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| Format |
application/pdf
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| Identifier |
http://ceeri.csircentral.net/607/1/38-2018.pdf
Singhal, N and Santosh, M and Bose, SC (2019) Reconfigurable Digital Logic Gate based on Neuromorphic Approach. In: 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID-2019), January 5-9, 2019, New Delhi, India. |
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| Relation |
http://ceeri.csircentral.net/607/
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