Generation and Annihilation of Process Induced Deep Level Defects in MOS Structures
IR@CEERI: CSIR-Central Electronics Engineering Research Institute, Pilani
View Archive Info| Field | Value | |
| Title |
Generation and Annihilation of Process Induced Deep Level Defects in MOS Structures
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| Creator |
Shashank, N
Gupta, SK Singh, V Akhtar, J Nahar, RK Damle, R |
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| Subject |
Sensors and Nanotechnology
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| Description |
The deep-level traps in Si substrates induced during the processing of Ni/ SiO2/n-Si have been investigated using deep level transient spectroscopy (DLTS). A deep level trap was detected at EC -0.49 eV, which was estimated to beintroduced during high temperature thermal oxidation process. The trap position was found to shift to different energy levels (Ec-0.43 eV, Ec-0.46 eV and Ec-0.34eV) during annihilation process. The deep level traps completely annealed at 350oC. Significant reduction in trap density with a systematic increase in recombination life time and the substrate doping concentration as a function of isochronal annealing were observed. The relevant details are discussed in this paper.
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| Date |
2010
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| Type |
Conference or Workshop Item
PeerReviewed |
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| Format |
application/pdf
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| Identifier |
http://ceeri.csircentral.net/82/1/68_2009%28i%29.pdf
Shashank, N and Gupta, SK and Singh, V and Akhtar, J and Nahar, RK and Damle, R (2010) Generation and Annihilation of Process Induced Deep Level Defects in MOS Structures. In: National Conference on Electronic Technology (ECT 2010), April 16-17, 2010, Goa, India. (Submitted) |
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| Relation |
http://ceeri.csircentral.net/82/
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