Silicon Nanowire Arrays using g-line Photolithography
IR@CEERI: CSIR-Central Electronics Engineering Research Institute, Pilani
View Archive Info| Field | Value | |
| Title |
Silicon Nanowire Arrays using g-line Photolithography
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| Creator |
Prajesh, R
Agarwal, A |
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| Subject |
MEMS and Microsensors
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| Description |
1 and 2 micron wide silicon fin patterns realized
using standard g-line UV lithography are oxidized to accomplish nanowires. Simulation results envisage the possibility of silicon nanowire fabrication using top down fabrication approach. Silicon consumption from three sides of the fins reduces their geometries. Stress developed in the oxide leads to a pinch-off in the fins with aspect ratios >3. This pinch-off divides the fin patterns into two parts vertically; upper part converges into silicon Nanowire, buried in silicon oxide. Simulation results for
different process temperatures, time and fin aspect ratios are presented in the paper.
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| Date |
2011
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| Type |
Conference or Workshop Item
PeerReviewed |
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| Format |
application/pdf
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| Identifier |
http://ceeri.csircentral.net/164/1/20_2011%282%29.pdf
Prajesh, R and Agarwal, A (2011) Silicon Nanowire Arrays using g-line Photolithography. In: 16th International Workshop on the Physics of Semiconductor Devices (IWPSD - 2011), December 19 - 22, 2011, IIT Kanpur, India. (Submitted) |
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| Relation |
http://ceeri.csircentral.net/164/
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