Analysis of Extended Pile Gate Trapezoidal Bulk FinFET
IR@NPL: CSIR-National Physical Laboratory, New Delhi
View Archive Info| Field | Value | |
| Title |
Analysis of Extended Pile Gate Trapezoidal Bulk FinFET
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| Creator |
Mangesh, Sangeeta
Chopra, P. K. Saini, K. K. |
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| Subject |
Electronics and Electrical Engineering
Telecommunications |
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| Description |
With technology scaling, innovative approaches in the device design are increasingly being explored. Improving device design is one of the focus areas for meeting the demand for low power high-speed circuit design. FinFET being the most promising device structure within the nanoscale regime, different structure variants of FinFET have been proposed and successfully implemented. In this paper, bulk FinFET device design is modified with a new design approach. Two different Si bulk trapezoidal FinFET devices, one with stacked gate and another with extended stacked gate are implemented using the 3D TCAD tool. The improvement in the performance metrics is denoted after comparing it with a simple trapezoidal Bulk FinFET device. Investigated performance metrics include subthreshold slope, Drain-Induced Barrier Lowering, Leakage Current, transconductance generation factor and threshold voltage and internal capacitance across Gate-Substrate, Gate-Drain and Gate -Source terminals of the device.
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| Publisher |
Medknow Publications
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| Date |
2019-03-18
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| Type |
Article
PeerReviewed |
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| Format |
application/pdf
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| Identifier |
http://npl.csircentral.net/4102/1/Analysis%20of%20Extended%20Pile%20Gate.pdf
Mangesh, Sangeeta and Chopra, P. K. and Saini, K. K. (2019) Analysis of Extended Pile Gate Trapezoidal Bulk FinFET. IETE Journal Of Research . pp. 1-7. ISSN 0377-2063 |
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| Relation |
http://npl.csircentral.net/4102/
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