Exploring Low Power Design Through Performance Analysis of FinFET for Fin Shape Variations
IR@NPL: CSIR-National Physical Laboratory, New Delhi
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| Title |
Exploring Low Power Design Through Performance Analysis of FinFET for Fin Shape Variations
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| Creator |
Mangesh, Sangeeta
Chopra, P. K. Saini, K. K. Saini, Amit |
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| Subject |
Construction & Building Technology
Automation & Control Systems |
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| Description |
With concern of global warming, low power design is an important research domain for scientist and engineers. Focusing upon the energy saving trend, this paper compares the performance analysis of all possible fin shapes in a 16 nm Bulk FinFET device from low power design perspective. Performance metrics include transconductance, transconductance generation factor (TGF), on/off current ratio, Subthreshold swing (SS), Drain Induced Barrier Lowering (DIBL) and power consumption. Low power system design feasibility with the optimized round fin shape resulting from the comparative analysis is justified by implementing N and P FinFET devices with perfectly matched VI characteristics. Prospective usage to meet recent developments in system design and control engineering with power optimization and scalability success in round FinFET device is also reviewed through this work.
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| Publisher |
Springer Verlag
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| Date |
2019
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| Type |
Article
PeerReviewed |
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| Format |
application/pdf
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| Identifier |
http://npl.csircentral.net/4195/1/Exploring%20Low%20Power%20Design.pdf
Mangesh, Sangeeta and Chopra, P. K. and Saini, K. K. and Saini, Amit (2019) Exploring Low Power Design Through Performance Analysis of FinFET for Fin Shape Variations. Advances in Intelligent Systems and Computing, 757. pp. 513-524. ISSN 2194-5357 |
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| Relation |
http://npl.csircentral.net/4195/
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