A VLSI Implementation of the PRESENT Cipher for System-on-Chip Applications
IR@CEERI: CSIR-Central Electronics Engineering Research Institute, Pilani
View Archive Info| Field | Value | |
| Title |
A VLSI Implementation of the PRESENT Cipher for System-on-Chip Applications
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| Creator |
Pandey, JG
Karmakar, A |
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| Subject |
IC Design
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| Description |
Fundamental essence of internet-of-things (IoT)
infrastructure is based on the security of communicated data. Here, lightweight cryptography plays a vital role in resource-constrained environments and applications. In this paper, we proposed a resource-efficient VLSI architecture for the PRESENT lightweight block cipher algorithm. The architecture is based on 8-bit datapath. An ASIC implementation of the proposed architecture is done by in SCL 0.18 µm technology. Here, the chip
operates on 3.3 V and the core works at 1.8V. Gate equivalent (GE) of the proposed architecture is 1608 GEs. At 100 MHz operating frequency, total power consumption of the chip is 2.45 mW, where, the dynamic component is 2.452 mW and the static one is 3.26µW. A throughput of 16.326 Mbps, energy 1.202 µJ, energy/bit 0.150 µJ /bit, and 0.010 efficiency is obtained. Area of chip is 1.55 mm2.
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| Date |
2020
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| Type |
Conference or Workshop Item
PeerReviewed |
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| Format |
application/pdf
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| Identifier |
http://ceeri.csircentral.net/542/1/432019.pdf
Pandey, JG and Karmakar, A (2020) A VLSI Implementation of the PRESENT Cipher for System-on-Chip Applications. In: 33rd International Conference on VLSI Design & 19th International Conference on Embedded Systems, January 04-08, 2020, Banglore, Karnataka. |
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| Relation |
http://ceeri.csircentral.net/542/
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