24 Bit seismic processor for analyzing extra large dynamic range signals for early warnings
IR@NISCAIR: CSIR-NISCAIR, New Delhi - ONLINE PERIODICALS REPOSITORY (NOPR)
View Archive Info| Field | Value | |
| Creator |
Kumar, Satish
Sharma, B K Sharma, Parkhi Shamshi, M A |
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| Date |
2009-04-13T04:01:53Z
2009-04-13T04:01:53Z 2009-05 |
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| Identifier |
0022-4456
http://hdl.handle.net/123456789/3788 |
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| Description |
372-378
Modified design is presented of existing 24 bit seismic data recorder comprising PC –architecture using PCI bus, ISA bus, and PC 104 bus in a single module to develop a flexible measurement set up. Paper elaborates use of building blocks [Disk on chip (DoC), GPS based timing unit, signal-processing module, and efficient software packages] worked out in visual C++ to develop compact sized instrument for quick decision-making with minimum error detection of true events. Paper describes Ethernet connectivity use for data downloading in a laptop without interruption of event data acquisition. Software packages for conversion of recorded data into SUDS and SEISAN formats have been realized and incorporated. |
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| Language |
en_US
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| Publisher |
CSIR
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| Source |
JSIR Vol.68(05) [May 2009]
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| Subject |
24 Bit seismic processor
Digital seismograph Early warning Earthquake Seismic Alert System |
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| Title |
24 Bit seismic processor for analyzing extra large dynamic range signals for early warnings
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| Type |
Article
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